Methods for establishing electrical connections by drawing one or both of an element of an electrical connector and a contact toward the other

ABSTRACT

A method for establishing an electrical connection includes drawing at least one of a member of an electrical connector and a contact in communication with at least one device. The drawing may be affected nonrigidly. It may occur in a direction substantially normal to a plane of the semiconductor device. Attractive forces, such as magnetic attraction, may cause the drawing. The establishment of electrical connection in this manner may be used in stress testing of semiconductor devices or to otherwise establish an electrical connection between one or more semiconductor devices and a ground, or power source.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 10/035,738,filed Nov. 7, 2001, pending, which is a continuation of application Ser.No. 09/777,986, filed Feb. 6, 2001, now U.S. Pat. No. 6,340,302, issuedJan. 22, 2002.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to methods and apparatus for effectingwafer-level bum-in, or stress testing, of semiconductor devices and,more particularly, to apparatus and methods for establishing anelectrical connection between semiconductor devices on a wafer or othersubstrate including multiple semiconductor devices thereon and bum-intest equipment. Specifically, the present invention relates to apparatusand methods that employ a magnetic field to establish an electricalconnection between semiconductor devices carried upon a wafer or othersubstrate and burn-in test equipment.

2. Background of the Related Art

Once semiconductor devices have been fabricated, the semiconductordevices or representative samples thereof are typically subjected to aseries of tests. These tests are intended to determine whether thesemiconductor devices will meet various performance and reliabilitystandards.

Stress testing, or burn-in testing, is one of the various types of teststhat may be performed on semiconductor devices. Stress testing typicallyinvolves the application of a substantial amount of current to one ormore semiconductor devices over a prolonged period of time and at anincreased temperature or with varied temperature. For example, about 10milliamps (mA) of current may be applied to each semiconductor devicecarried upon a substrate as the temperature of the semiconductor deviceis cycled between ambient temperature and a temperature of at leastabout 100° C. Such cycling of the temperature of the semiconductordevice as current is being applied thereto is intended to stress thesemiconductor device by driving any contaminants therein into the activecircuitry thereof, thus causing failure of the semiconductor device.This type of stress testing is known in the art to cause the earlyfailure of unreliable semiconductor devices, thereby preventing theseunreliable semiconductor devices from being sold and used. As a result,semiconductor devices that pass such stress testing are typically morereliable than those which fail such stress tests.

Conventionally, stress testing equipment has included a carrierconfigured to hold one or more semiconductor devices during testing anda burn-in oven within which stress testing is conducted. Various typesof carriers have been developed, including carriers for single, bare orpackaged semiconductor devices, as well as wafer carriers. The carriersmay include electrically conductive structures, such as pins, thatcontact the bond pads of each semiconductor device held by the carrierso as to apply an electrical current or a voltage to each semiconductordevice held by the carrier.

Wafer carriers may alternatively be configured to establish anelectrical connection with a multiplicity of semiconductor devicescarried upon a wafer or other substrate by contacting one or more commoncontact locations formed on the wafer or other substrate. For example,it is known in the art to fabricate wafers with each of thesemiconductor devices carried thereon in communication with a commonground contact and a common power (V_(CC)) contact, which are alsocarried upon the wafer. Conventionally, electrical connection of thecommon ground contact and the common power (V_(CC)) contact of such awafer to ground and a power (V_(CC)) source, respectively, has beeneffected by use of clamping mechanisms, such as C-clamps or so-called“alligator clips” with planar conductive plates thereon.

When alligator clips are used to establish an electrical connectionbetween the semiconductor devices on a wafer and a ground or a powersource, a radial tangent force is applied to the substantially flatactive surface and backside of the wafer at the locations of the groundcontact and the power (V_(CC)) contact. While a low resistanceelectrical contact is established by use of such alligator clips, theradial tangent force applied by an alligator clip may cause theconductive plates on the alligator clip to contact only a small area ofthe respective contact formed on the active surface of the wafer and theopposing backside of the wafer. As a result, a large amount of pressuremay be applied to a small area on the wafer, which may cause damage tothe wafer that may, in turn, damage semiconductor devices carried by thewafer. In addition, as the temperature of the burn-in oven is increased,the alligator clips may expand and, thus, be moved along the wafer,which may also damage the wafer, as well as the semiconductor devicesformed thereon.

While C-clamps contact larger areas of the respective common ground andpower (V_(CC)) contacts formed on the active surface of a wafer, as wellas larger areas on the backside of the wafer, and apply force to thewafer in a direction substantially normal, or perpendicular, to theplane of the wafer, C-clamps are relatively clumsy and would, therefore,likely increase the chance that a wafer is damaged as C-clamps aresecured to their respective contacts. Moreover, when stress testinginvolves varied temperatures, the expansion of a C-clamp would increasethe amount of force applied to the wafer, which could crack or otherwisedamage the wafer, as well as semiconductor devices carried upon thewafer. Conversely, contraction of a C-clamp during cooling could resultin an inadequate electrical connection between the C-clamp and itscorresponding contact.

Due to the material expansion that typically occurs with the temperaturevariations of burn-in testing, the direction at which contact force isapplied to a substrate by both alligator clips and C-clamps may deviatefrom normal (i.e., from a direction that is perpendicular to the planeof the substrate). As is known in the art, deviations in contact forcemay cause similar deviations in contact resistance. Even a small changein contact resistance may translate into a substantial drop in thevoltage supplied (V_(CC)) to each semiconductor die on the substrate.For example, when the substrate is a wafer that carries 500semiconductor dice, about 5 amps (A) of current are applied to the powersupply (V_(CC)) contact of the substrate, or about 10 mA is supplied toeach of the 500 dice. As calculated in accordance with Ohm's law, asmall, 20 milliohms (mΩ) increase in the contact resistance between anelectrical connector of the burn-in test equipment and a common contacton the substrate would cause a substantial, 100 mV decrease in thevoltage (V_(cc)) applied to the dice through the common contact. Thus,the amount of power and voltage applied to each die during wafer-levelburn-in testing may not be consistent or repeatable when alligator clipsor C-clamps are used to supply a burn-in voltage to dice through acommon contact on the wafer or other substrate.

No known apparatus or method for establishing an electrical contact witha common contact on a wafer is available which does not induce stress onor in the wafer. No known apparatus or method in wafer-scale stresstesting of semiconductor devices is available without applying too muchforce or too little force to the wafer.

BRIEF SUMMARY OF THE INVENTION

The present invention includes an electrical connector configured toestablish an electrical connection between a ground or a power (V_(CC))source and a common contact formed on a wafer without applying apotentially damaging amount of force to the wafer. The present inventionalso includes methods for assembling a wafer or other semiconductorsubstrate with stress testing equipment, as well as methods forwafer-level stress testing of semiconductor devices.

An electrical connector incorporating teachings of the present inventionmay include two opposed members, or contact plates, each of which isconfigured to be positioned against a surface of a wafer or othersemiconductor substrate. In use, the two members of an electricalconnector of the present invention are positioned on correspondinglocations of opposite sides of a wafer or other semiconductor substrateand apply opposing forces to the wafer or other semiconductor substratein directions normal to a plane of the wafer or other semiconductorsubstrate. The amounts of opposing force may be substantially equal.Accordingly, at least one of the two opposed members may include anattractive element, such as a magnet, which attracts a correspondingelement of the oppositely positioned member. The corresponding elementmay, therefore, include a magnet of opposite polarity or a material,such as an iron-containing material, that may be attracted to a magneticfield. In addition, the electrical connector member that is to be biasedagainst a common contact formed on the wafer or other semiconductordevice includes an electrically conductive element, while the other,opposite member of the electrical connector may include an electricallynonconductive support element configured to engage a backside of thewafer or other semiconductor substrate. The support element may also beconfigured to cushion the backside of the semiconductor substrate.

A method for establishing an electrical connection in accordance withteachings of the present invention includes positioning a first memberof an electrical connector in electrically conductive contact with acontact of a semiconductor device structure, such as a wafer, anothersubstrate carrying a plurality of semiconductor devices, or a singlesemiconductor device. A second member of the electrical connector ispositioned in a corresponding location on an opposite side of thesemiconductor device structure. The first and second members of theelectrical connector nonrigidly apply opposed force to the semiconductordevice structure in directions substantially normal to a plane of thesemiconductor device structure. The amounts of opposed force applied tothe semiconductor device structure by the first and second members arepreferably substantially equal. Preferably, the amounts of force appliedby the first and second members of the electrical connector to thesemiconductor device structure are also sufficient to establishelectrical communication between the first member and the contactwithout inducing potentially damaging stresses in the semiconductordevice structure. The opposed forces may be generated by magneticattraction of the first and second elements of the electrical connectorto one another, by other known, nonrigid attractive forces, or by othernonrigid securing means for forcing two objects directly toward oneanother.

A method for stress testing semiconductor devices in accordance withteachings of the present invention includes nonrigidly securing a firstelectrical connector of the present invention to a ground contact incommunication with the semiconductor device and nonrigidly securing asecond electrical connector of the present invention to a power (V_(CC))contact in communication with the semiconductor device, with the firstand second electrical connectors each being biased against theirrespective contacts in a direction substantially normal to a plane ofthe semiconductor device. The stress testing method also includesestablishing communication in between the first electrical connector anda ground and establishing communication between the second electricalconnector and a power (V_(CC)) source, or supply. In addition, stresstesting in accordance with teachings of the present invention includesexposing the semiconductor device to an increased temperature or varyingthe temperature of the semiconductor device, such as by cycling thetemperature of the semiconductor device, increasing the temperature ofthe semiconductor device, or decreasing the temperature of thesemiconductor device.

Other features and advantages of the present invention will becomeapparent to those of ordinary skill in the art through a considerationof the ensuing description, the accompanying drawings, and the appendedclaims.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

In the drawings, which illustrate exemplary embodiments of the presentinvention:

FIG. 1 is a schematic representation of a semiconductor wafer includinga plurality of semiconductor devices fabricated thereon, eachsemiconductor device communicating with both a common ground contact anda common power (V_(CC)) contact, which are also fabricated on thesemiconductor wafer;

FIG. 2 is a perspective assembly view of an electrical connectorembodying teachings of the present invention electrically connected tothe semiconductor wafer shown in FIG. 1;

FIG. 3 is a cross-sectional representation taken along line 3-3 of FIG.2;

FIG. 3A is a cross-sectional representation illustrating variations ofthe members of electrical connectors incorporating teachings of thepresent invention;

FIG. 4 is a schematic representation of a stress testing, or burn-in,process according to the present invention; and

FIG. 5 is a cross-sectional representation of an embodiment of a Kelvinconnector incorporating teachings of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

A semiconductor wafer, referred to herein as a substrate 10, whichincludes a plurality of semiconductor devices 14 carried upon an activesurface 11 thereof, is illustrated in FIG. 1. Substrate 10 alsoincludes, on active surface 11, a common ground contact 16 and a commonpower (V_(CC)) contact 18. Common ground contact 16 and common power(V_(CC)) contact 18 both communicate with a number of differentsemiconductor devices 14 on substrate 10 by way of respective circuittraces 17, 19 carried upon active surface 11 of substrate 10. Althoughsubstrate 10 is illustrated in FIG. 1 as a semiconductor wafer, thehereinafter described electrical connector of the present invention maybe used with other substrates, including, without limitation, individualsemiconductor dice, full or partial wafers formed of semiconductivematerial (e.g., silicon, gallium arsenide, iridium phosphide, etc.), andsilicon-on-insulator (SOI) substrates, such as silicon-on-glass (SOG),silicon-on-sapphire (SOS), and silicon-on-ceramic (SOC).

Referring now to FIGS. 2 and 3, an exemplary embodiment of an electricalconnector 20 incorporating teachings of the present invention isillustrated. Electrical connector 20 includes a first member 22 and asecond member 24. As illustrated, first member 22 is configured toestablish an electrical connection with each contact 16, 18 of asubstrate 10. Second member 24 is configured to engage backside 12 ofsubstrate 10 in a manner that nonrigidly draws first member 22 againstcontact 16, 18 in a direction that is substantially normal, orperpendicular, to a plane of substrate 10, as indicated by arrow N.

With continued reference to FIGS. 2 and 3, first member 22 of electricalconnector 20 includes an electrically conductive element 26 with asubstantially planar contact surface 27 configured to engage a contact16, 18 of a substrate 10. First member 22 also includes a firstattractive element 28.

Electrically conductive element 26 is preferably formed from a suitableconductive material that will have sufficiently low contact resistancewith the material of contacts 16, 18 so as to facilitate the applicationof a suitable voltage to each semiconductor device 14 in communicationwith contacts 16, 18 while minimizing the amount of power dissipated bythe interface of contact 16, 18 and an electrically conductive element26 contacting same. Preferably, the contact resistance betweenelectrically conductive element 26 and contacts 16, 18 is about 100 mΩor less. By selecting a conductive material that will have such lowcontact resistance with a material of contacts 16, 18, the likelihoodthat substrate 10 will be heated to an excessive temperature byelectrical resistance at the interface between a contact 16, 18 and anelectrically conductive element 26 is reduced. The likelihood thatsubstrate 10 will be damaged by excessive temperatures is also reducedwhen the contact resistance between the material of electricallyconductive element 26 and contact 16, 18 is low. Exemplary materialsthat may be used to form electrically conductive element 26 include,without limitation, gold, nickel, copper, tungsten, or an alloyincluding any of these materials. Electrically conductive element 26 isconfigured to communicate with one of a ground 50 and a power (V_(CC))source 52 to form at least a portion of a circuit including power(V_(CC)) source 52, at least one semiconductor device 14 on substrate10, and ground 50.

First attractive element 28 is configured to attract or to be attractedby a corresponding, second attractive element 38 of second member 24 ofelectrical connector 20. By way of example, and not to limit the scopeof the present invention, first attractive element 28 and secondattractive element 38 may be magnetically attracted to one another.Accordingly, in this example, first attractive element 28 may comprise,but is not limited to, a magnetic material, an electromagnet, or amaterial that is attracted to a magnetic field (e.g., iron or aniron-containing material). Alternatively, first attractive element 28may include an electrically nonconductive matrix impregnated withparticles of magnetic material.

In alternative embodiments, the electrically conductive and attractiveelements of an electrical connector incorporating teachings of thepresent invention may be fully or partially combined. As shown in FIG.3A, an electrical connector 20′ includes a first member 22′ with acombined electrically conductive/attractive element 26′/28′. Combinedelement 26′/28′ may comprise a matrix material 30′ impregnated withelectrically conductive, Z-axis type filaments, or particles 31′, andattractive particles 29′. Upon positioning first member 22′ withcombined element 26′/28′ in contact with a common contact 16, 18(FIG. 1) of a substrate 10, an electrical connection is establishedbetween first member 22′ and one or more semiconductor devices 14(FIG. 1) on substrate 10. Matrix material 30′ may be a relatively soft,pliable material, such as silicone or another elastomer, so as toprevent common contact 16, 18 from being damaged as first member 22′ ispositioned thereagainst.

With returned reference to FIGS. 2 and 3, second member 24 of electricalconnector 20 includes a support element 36 with second attractiveelement 38 coupled thereto. Support element 36 is configured to engagebackside 12 of substrate 10, opposite from the location at which firstmember 22 is positioned over active surface 11. Support element 36includes a contact surface 37, which is preferably planar so as tofacilitate the application of force against backside 12 in a directionthat is substantially normal, or perpendicular, to a plane of substrate10. Support element 36, including contact surface 37 thereof, may beformed from any suitable, substantially rigid material to facilitate theapplication of force against backside 12 of substrate 10. For example,but not to limit the scope of the present invention, support element 36may be formed from an electrically conductive material (e.g., the samematerial as that employed to form contact surface 27 of electricallyconductive element 26 of first member 22 of electrical connector 20) oran electrically nonconductive material (e.g., glass, ceramic, a resin,or an elastomer). As shown, contact surface 37 may be coated or linedwith a softer, more pliable material, such as silicon or anotherelastomer, to cushion and to prevent damage to substrate 10 aselectrical connector 20 is secured thereto, as well as to electricallyinsulate second member 24 of electrical connector 20 from backside 12 ofsubstrate 10.

Second attractive element 38 of second member 24 is configured toattract or to be attracted by the corresponding first attractive element28 of first member 22. Accordingly, if first attractive element 28comprises an electromagnet or a magnetic material, second attractiveelement 38 may comprise a magnet or electromagnet of opposite polarityor a material (e.g., iron or an iron-containing material) that isattracted to a magnetic field. Alternatively, if first attractiveelement 28 comprises a material that is attracted to a magnetic field,second attractive element 38 may comprise a magnetic material or anelectromagnet.

A variation of a second member 24′ of an electrical connector 20′incorporating teachings of the present invention includes a combinedsupport element/attractive element 36′/38′, as illustrated in FIG. 3A.As depicted, combined element 36′/38′ includes a matrix material 40′impregnated with particles 39′ of attractive material. As in theexamples provided previously herein, attractive particles 39′, may bemagnetically attracted to an attractive element 28, 28′ of acorresponding first member 22, 22′. Accordingly, depending upon thematerial used in attractive element 28, 28′, attractive particles 39′may comprise a magnetic material or a material that is attracted to amagnetic field. Matrix material 40′ may comprise either a rigidmaterial, such as an elastomer or a resin, or a softer, more pliablematerial, such as silicone or another soft elastomer.

With reference to FIG. 5, a Kelvin connector 20″ incorporating teachingsof the present invention is illustrated. Kelvin connector 20″ includes afirst member 22″ and a second member 24″. As illustrated, first member22″ is configured to establish two separate electrical connections witheach contact 16, 18 of a substrate 10. Second member 24″ is configuredto engage backside 12 of substrate 10 in a manner that nonrigidly drawsfirst member 22″ against contact 16, 18 in a direction that issubstantially normal, or perpendicular, to a plane of substrate 10, asindicated by arrow N.

As the electrical connector depicted in FIG. 5 is a Kelvin connector,first member 22″ includes two electrically conductive elements 26 a″, 26b″, one of which (e.g., electrically conductive element 26 a″) applies acurrent to a substrate 10, the other of which (e.g., electricallyconductive element 26 b″) facilitates monitoring, by a monitoring device56 of a known type, of the current and/or voltage applied to substrate10. Each electrically conductive element 26 a″, 26 b″ may be configuredas described previously herein with respect to conductive elements 26illustrated in FIGS. 2 and 3. First member 22″ also includes a firstattractive element 28″.

Second member 24″ of Kelvin connector 20″ may be configured aselectrical connector 20 illustrated in FIGS. 2 and 3 and describedherein with reference to FIGS. 2 and 3. Accordingly, second member 24″facilitates the securing of first member 22″ to a contact 16, 18 ofsubstrate 10 by nonrigidly attracting first member 22″ against substrate10 in a direction substantially normal to a plane of substrate 10.

Kelvin connector 20″ facilitates the monitoring of a current and/orvoltage that is applied to one or more semiconductor devices, as well asthe adjusting of such current and/or voltage. Accordingly, when Kelvinconnector 20″ is used to establish an electrical connection with one ormore semiconductor devices, such as in stress, or burn-in, testing, adesired, appropriate amount of current and/or voltage may be applied toone or more semiconductor devices 14 over a specified duration of time.If the current and/or voltage shifts, such shifts may be monitored andappropriate adjustments may be made, as known in the art.

Referring again to FIGS. 2 and 3, an example of the use of electricalconnector 20 to establish electrical communication with a contact 16 ofa substrate 10 is illustrated. First member 22 of electrical connector20 is positioned over contact 16 and electrically conductive element 26thereof is brought into contact with contact 16. Second member 24 ispositioned under backside 12 of substrate 10 in a location opposite theposition of contact 16 on active surface 11. Once both first and secondmembers 22, 24 have been appropriately positioned, a nonrigid attractiveforce between first member 22 and second member 24 secures both firstand second members 22, 24 to substrate 10 in such a manner thatelectrically conductive element 26 of first member 22 will electricallycommunicate with contact 16. For example, without limiting the scope ofthe present invention, magnetic attraction between first and secondmembers 22, 24 or elements thereof may secure first and second members22, 24 to opposite sides of substrate 10. Preferably, the attractiveforces are sufficient to maintain an adequate electrical contact betweenelectrically conductive element 26 of first member 22 and contact 16 ofsubstrate 10 without stressing substrate 10 to a degree that may damagesubstrate 10 or any semiconductor devices 14 carried thereby. Inaddition, due to the planar contacting surfaces 27, 37 of electricallyconductive element 26 and support element 36, respectively, theattractive forces between attractive elements 28 and 38 are applied tosubstrate 10 in directions that are substantially normal to a planethereof.

In an exemplary use of an electrical connector 20 incorporatingteachings of the present invention, electrical connectors 20 or otherelectrical connectors according to the invention that communicate witheach of a ground 50 and a power (V_(CC)) source 52 may be nonrigidlysecured to substrate 10 so as to communicate with contacts 16, 18 that,in turn, communicate with one or more semiconductor devices 14 to bestress tested. Upon securing electrical connectors 20 to substrate 10 insuch a manner, both members 22, 24 of electrical connector 20 applyforce to substrate 10 in a direction that is substantially normal to aplane of substrate 10.

As shown in FIG. 4, substrate 10 and electrical connectors 20 securedthereto are placed within a burn-in oven 60. A preferably substantiallyconstant electrical current is then applied to each semiconductor device14 carried by substrate 10 through electrical connectors 20 and thetemperature of burn-in oven 60 is increased. The temperature of burn-inoven 60 may be increased to a substantially steady temperature or may bevaried, as is known in stress testing of semiconductor devices. Forexample, with reference to FIG. 1, when substrate 10 is a waferincluding a plurality of semiconductor devices 14, such as dynamicrandom access memory (DRAM) devices or static random access memory(SRAM) devices and includes common contacts 16, 18 for connection ofeach semiconductor device 14 on substrate 10 to a ground 50 and a power(V_(CC)) source 52, such as that depicted in FIG. 1, sufficient current(e.g., about 6-10 amps) is applied to contacts 16, 18 of substrate 10 topermit each semiconductor device 14 carried thereby to draw about 10 mA.In addition, the temperature of burn-in oven 60 may be cycled during thestress testing process. Of course, electrical connectors incorporatingteachings of the present invention, as well as methods of the presentinvention may also be used to facilitate electrical connections in othertesting and use applications.

Although the foregoing description contains many specifics, these shouldnot be construed as limiting the scope of the present invention, butmerely as providing illustrations of selected, preferred embodiments.Similarly, other embodiments of the invention may be devised which donot depart from the spirit or scope of the present invention. The scopeof this invention is, therefore, indicated and limited only by theappended claims and their legal equivalents, rather than by theforegoing description. All additions, deletions and modifications to theinvention, as disclosed herein, which fall within the meaning and scopeof the claims are embraced within their scope.

1. A method for establishing a temporary electrical contact with atleast one semiconductor device, comprising: drawing at least one of afirst member of an electrical connector and a contact that is inelectrical communication with at least one semiconductor device towardthe other of the first member and the contact to establish a temporaryelectrical contact between the first member and the contact.
 2. Themethod of claim 1, wherein drawing is effected in a directionsubstantially normal to a plane of the contact.
 3. The method of claim1, wherein drawing is effected in a direction substantially normal to aplane of a substrate upon which the contact is carried.
 4. The method ofclaim 1, wherein drawing is effected by positioning a second member ofthe electrical connector opposite the first member.
 5. The method ofclaim 4, wherein drawing is effected by attracting at least one of thefirst member and the second member toward at least the other of thefirst member and the second member.
 6. The method of claim 4, whereindrawing comprises securing the first and second members to a substrateupon which the contact is carried.
 7. The method of claim 1, whereindrawing comprises securing the first member to the contact.
 8. Themethod of claim 1, wherein drawing comprises magnetically drawing. 9.The method of claim 1, further comprising: permitting an electricalcurrent to flow from at least one of the electrical connector and thecontact to the other of the contact and the electrical connector as thetemporary electrical contact is maintained
 10. A method for stresstesting a plurality of semiconductor devices carried upon a commonsubstrate and in communication with common ground and power contacts,comprising: drawing at least one of a first member of an electricalconnector and at least one contact of a ground contact and a powercontact toward the other of the first member and the at least onecontact to establish and maintain a temporary electrical contact betweenthe first member and the at least one contact.
 11. The method of claim10, wherein drawing is effected in a direction substantially normal to aplane of the common substrate.
 12. The method of claim 10, whereindrawing nonrigidly biases the first member against the at least onecontact.
 13. The method of claim 10, wherein drawing comprisespositioning a second member of the electrical connector opposite thesubstrate from the first member.
 14. The method of claim 13, wherein atleast one of the first member and the second member is drawn toward atleast the other of the first member and the second member.
 15. Themethod of claim 14, wherein drawing comprises attracting at least one ofthe first member and the second member toward at least the other of thefirst member and the second member.
 16. The method of claim 10, whereindrawing comprises securing the first member to the at least one contact.17. The method of claim 10, wherein drawing comprises securing at leastthe first member in position relative to the substrate.
 18. The methodof claim 10, wherein drawing comprises magnetically drawing.
 19. Themethod of claim 10, further comprising: permitting an electrical currentto flow from at least one of the electrical connector and the contact tothe other of the contact and the electrical connector as the temporaryelectrical contact is maintained
 20. The method of claim 10, furthercomprising: electrically connecting another first member of anotherelectrical connector to another of the ground contact and the powercontact; and drawing the another first member toward the anothercontact.
 21. The method of claim 20, further comprising: applying asubstantially constant amount of current to each semiconductor device ofthe plurality of semiconductor devices through the first member and theanother first member.
 22. The method of claim 21, further comprising:heating each of the plurality of semiconductor devices.
 23. The methodof claim 22, wherein heating comprises cycling a temperature of each ofthe plurality of semiconductor devices.
 24. The method of claim 22,wherein heating comprises varying a temperature of each of the pluralityof semiconductor devices.